Tiger Lake and Rocket Lake have recently been a hot topic since both are very likely to launch this year (Rocket Lake might slip to early 2021) and because these two CPUs might represent a significant shift in Intel’s hardware in terms of not just node but also architecture. We have previously reported that Rocket Lake would feature a dedicated 10nm GPU with Gen 12 Xe Graphics, but the CPU cores are also interesting because some rumors suggest it is a backport of the 10nm Willow Cove cores found on 10nm.
The most important leaker behind these Tiger Lake and Rocket Lake rumors has been Sharkbay, who initially suggested Rocket Lake would use backported Willow Cove cores on 14nm. This theory has been heavily scrutinized because a core backport isn’t entirely feasible, but Sharkbay has remained confident in this claim. In his most recent leak, Sharkbay asserts that Rocket Lake must use either the Sunny Cove or Willow Cove core because of its L1 and L2 cache structure.
…one of the features of the Cove series uArch is the asymmetrical L1 cache sizes (32K+48K). As for which generation of Cove, I can’t tell from the MLC [cache hierarchy]…
Sharkbay, translated by @chiakokhua
It isn’t a trivial thing to change a core’s L1 and L2 cache since they are literally right in the core; it’s not nearly as simple as when AMD decided to double L3 cache when going from Zen to Zen 2. If Rocket Lake does have an identical cache structure to Tiger Lake, then that strongly implies a backport or at the very least some sort of architectural rework that is far more substantial than anything Intel has done since 2017 with Skylake X. Though I personally am skeptical of this backport theory, it’s not entirely without evidence. At the very least, it’s possible Rocket Lake won’t be using the same cores as all the Skylake rehashes. It might even use some 10nm IP without being a complete backport.
Additionally, Sharkbay also suggested Tiger Lake H would come with up to 8 cores, which would bring 10nm CPUs up to parity with 14nm CPUs on mobile in terms of core count. This CPU is a 45 watt class part, but as for actual power consumption and efficiency it’s difficult to tell where it lands since Intel’s TDP rating means even less than AMD’s (the 9900K is apparently a 95 watt part, for instance). While Intel added 4 more cores, they seem to have reduced the graphics from “GT2” to “GT1”, a naming scheme which Rocket Lake and Alder Lake follow for their graphics solutions. That would at least imply that the iGPUs of these three architectures share the same specifications, but it might also mean that they’re all using the same 10nm dedicated graphics die used on Rocket Lake. Still too early to know for sure, however.
Finally, it seems that Tiger Lake was actually supposed to support DDR5 memory but it appears this support was later dropped because AMD wouldn’t be on DDR5 at the time. This can make sense for three reasons. First, Intel doesn’t feel pressured to start using DDR5 because AMD isn’t, and they are only aiming for parity with AMD on memory support. Second, Intel might not want to be the only company in the world supporting DDR5, which could negatively affect their platforms using DDR5. Or third, Intel simply did not have enough time to make it work.
One last thing that Sharkbay mentioned was that both Tiger Lake and Rocket Lake could support “two level memory.” I searched around for that term and the only relevant result I came across was Knight’s Landing (one of the Xeon Phi archs and a remnant of Intel first GPU project) apparently using two level memory. I’m not sure how relevant that is here but it is a curious thing to note given how mysterious it is.