To answer the question from the article title, in short, “it depends” and cryptically “that’s not actually the question.”
News broke last week about TSMC’s 5nm yields surpassing 7nm yields at this point in its development cycle, with some outlets even (incorrectly) reporting 7nm was only at 50% yields currently. Of course, the news in this is rather straight-forward: 5nm development is going well, and is progressing better than 7nm did at this point in its development cycle. The big story in this, however, is more about what gets lost in translation when the news gets reported from original sources, or worse yet, second-hand reporting.
The story that seems to be cited as the source is from the China Times (and thus in Chinese, naturally), which you can translate and read for yourself here if you desire. The big takeaways are that Google translates some lines from this article as the following:
“Its [5nm] yield has reached 50% overtaking the initial 7-nanometer, including Apple.” “As for the yield, according to the supply chain, the 5nm yield has reached 50%.”
I, unfortunately do not speak Chinese, but I do understand the nuance involved with trying to read a foreign language through an automatic translator. However, a native Chinese speaker assures me that China Times was Google-translated fairly accurately.
Doing a few re-reads, I noticed there’s one crucial bit of information in the article, right before this whole “50%” bit, at the beginning of the paragraph:. “TSMC mentioned earlier…” This, of course, lead me to finding what I believe is the true root of this article: an article from GizChina, a gadget reviews site, which is in English, and is titled “TSMC’S 5NM PROCESS TRIAL PRODUCTION IS 50% COMPLETE,” which is reporting on this original TSMC news.
Let me copy a relevant paragraph: “The mass production should start from Q1 2019 [sic]. This time, it is about a quarter ahead of the normal mid-year mass production. This shows that the 5nm process is making good progress. According to the supply chain, the risk trial production is smoother tha[n] the previous generation. Over time, the yield of the 5nm process will gradually increase, especially during the mass production phase.”
Let’s compare this to the Google-translated version of the China Times article: “TSMC mentioned earlier that the 5nm process has been developed and entered the risk trial production stage. Mass production is expected as soon as the first quarter of next year. As for the yield, according to the supply chain, the 5nm yield has reached 50%.”
A bit of sentence reordering tells us they’re talking about the same thing: mass production in Q1 2020 (as GizChina’s article was written late October 2019, they’re obviously not talking about ramping up 5nm nine months prior…). Crucially, they compare vs 7nm as “smoother” trial production and that the yield will gradually increase as they move into mass production. There’s no mention of actual numbers, except in the article title, and that states completion percent, not “yields,” but happens to be that exact “50%” that’s being reported.
It seems there’s a lot of translation issues in this whole mess. Is it an issue from China Times? Perhaps the English version of GizChina’s article? Perhaps both translations are accurate and the news itself was just misreported like we’re seeingwith 7nm yield rates because of this China Times article.
Let me emphasize that “yield rate” is also very dependant on the size of die you’re trying to make. A 100mm² die will have a dramatically different yield rate compared to a 600mm² die on the exact same process node, simply due to defect density, let alone any errors encountered during the actual process. The articles suggest TSMC uses data based on a “Cortex A72” (ARM CPU, or maybe just a core) as its testing sample, which is a very small chip design. [Update: They used a 256 Mbit SRAM chip with 30% SRAM, 60% Logic and 10% IO, at a calculated estimated size of 17.92mm2]
We’ll know the truth soon enough however, as Dr. Ian Cutress, a very knowledgeable and trustworthy reporter over at Anandtech, seems to have actual data.
Note, he states “if you scale up the test chips, it’s nowhere near that,” which suggests the test chips are, indeed, very small.
I look forward to reading Ian’s paper when it becomes available, as it’s bound to be quite interesting. [Update: It’s available now, but projects defect rates compared to existing 7nm die sizes in provided examples, as opposed to those same dies shrunk to 5nm size, so they are still under-estimating yields at just 41% for a 76mm2 “Zen2 chiplet.” They do calculate a reasonable-sized 100mm2 “mobile” die would provide yields at 32%. Their miniscule test chip has yields at 80%.]
All of this serves as a good reminder to check the sources of what you read, read more than just the headlines for the whole story (as headlines are becoming quite sensationalized), and be sure to sanity-check what you do read to make sure it lines up with what we already know.
And in case you still don’t know the answer to the title question, the actual answer to the real question is trial production is 50% complete; at least it was back at the end of October.
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