You may recall our last Zen 3 leak which revealed three important details: L3 cache size would be unchanged from Zen 2 (doubled per CCX, however, due to unifying the dual CCX), overall IPC gains over Zen 2 would be between 10% and 15%, and Milan’s B0 stepping would come out in September. Recently, these details have mostly been confirmed by other publications and independent sources. Today, we’re following up on this leak with another leak about Zen 3.
Just a few days ago, Igor’s Lab leaked some OPN numbers and specifications that correspond to Milan engineering samples, and one thing to note is the L3 cache size. It is 256 MB large, the same as Rome, meaning AMD has not added any additional L3 to the CCD, just as we reported in March. However, L3 cache per CCX will be double because AMD has unified the two CCXs on a single CCD. In that sense, the L3 cache has been enlarged. We consider the L3 cache size of Zen 3 to be confirmed at this point.
Earlier, in May, Igor reported on some Zen 3 engineering samples they had come across, likely Vermeer samples since the clocks were high and the core count was low. These are A0 stepping CPUs, and if you recall in our March Zen 3 leak we said Milan A0 had SMT disabled. While Igor’s information seems contradictory, it should be pointed out that our info was reported in early April (however we received it in February) and referred to Milan whereas Igor reported this in mid to late May and referred to Vermeer.
Igor also leaked some more Zen 3 info back in June, this time about the B0 stepping which is likely the final or close to final stepping before mass production. This time there was a more direct contradiction in that the B0 stepping apparently already exists, whereas we reported that it was coming in September after a delay. We’re still confident in the source that informed us about Milan’s A0 and B0 steppings, so it seems likely to us that “B0 delayed until September” was actually about mass production and not chip development. Another one of our sources recently told us Milan is still ready for a December launch, so in any case B0 being developed in September is highly unlikely. We believe that Vermeer and Milan (since they share the same CCD) will be finished on their B0 steppings and will enter mass production in September.
We actually also have an updated version of AMD’s leaked Epyc 7000 series roadmap, which indicates even further that September is the month of B0’s production. In our updated version (which we sadly cannot show), the whole Milan graphic has been moved farther to the right so that the “production” text appears to land at the end of the Q3 column, rather than the middle of the column as you can see in the picture below. September is, of course, the last month of Q3. It seems as if this change was made for a reason.
Speaking of that roadmap, you can see it is unambiguous about Milan supporting DDR4 and PCIe 4, but back in October we speculated that AMD could technically make an IO die that brought DDR5 and PCIe 5 to Milan. The source that brought that possibility to our attention shared with us an AMD roadmap that showed DDR5 availability in Q3, before Micron had announced it. There have also been rumors about a variant of Milan referred to as “Milan HPC” with Milan chiplets but the Genoa IO die. We can’t confirm that rumor, but there does seem to be a possibility that a special version of Milan with DDR5 and/or PCIe 5 support exists.
Note: Following paragraph has been changed since publication for accuracy and clarity.
We also have some performance figures for Milan. It is over 20% faster in single threaded integer workloads compared to Rome, 20% faster in 32 core integer workloads, and between 10 and 15% faster in all core (that is 64 core) workloads. The decreased integer performance with increasing core counts could be signs of decreasing clock speed or some sort of architectural bottleneck being hit when more cores are loaded. Though some rumors have stated that Milan has a 50% floating point improvement, we don’t think this is the case. Most of the overall IPC improvement in Milan is likely integer related; on its own, the integer IPC gain is probably more than 15% and the floating point gain is probably less than 10%. We expect AMD will change their methodology for calculating IPC gain and focus more on integer workloads so that they can claim more than a 15% IPC gain. Should they calculate Zen 3’s IPC gain like Zen 2, we would expect a gain of 10-15%.
Some of our sources familiar with Intel’s Ice Lake server CPUs have also given us word that while Ice Lake is likely going to launch up to a month sooner than Milan, it probably won’t matter much given the performance. We were told that a 32 core Ice Lake server CPU at 2.5 GHz with a 250 watt TDP is probably the best Intel can muster. It is highly unlikely Intel can even compete against the 32 core Milan in any capacity.
In our opinion, Zen 3 is looking like a slam dunk for AMD. On the desktop, Vermeer based Ryzen 4000 looks like it will be around 20% faster than Matisse based Ryzen 3000. The unified CCX and L3 cache will reduce overall latency when using more than 4 cores, which strongly suggests that AMD will overtake Intel in gaming thanks to Zen 2’s greatest latency bottleneck being solved. On the server, Milan is likely to beat Ice Lake in the same way Rome beat Skylake and Cascade Lake (though we don’t think it’s going to have 50% higher floating point than Rome).
We actually have some more info left to share about upcoming tech, so keep an eye out for that.
