Exclusive: Intel Sapphire Rapids to Feature Chiplets, HBM2, 400 Watt TDP, Coming in 2021
Update: Intel reached out to request we take the article down on the grounds that our report was “inaccurate”. However when asked which part was “inaccurate” they either couldn’t or wouldn’t answer, without which we cannot remove the article. We believe the vast majority of the information here is factual at the time of writing. Some details might change over the course of the product’s development.
Intel’s upcoming Sapphire Rapids CPU architecture has been anticipated for some time in the server and datacenter space, and today we can share some of the most important specifications and even its release date. Though Sapphire Rapids is a 10nm(+++) product, it’s actually quite interesting and could be Intel’s first step in its plan to recommence competition with AMD.
Let’s talk about cores first. Sapphire Rapids will use the new Golden Cove core, which succeeds the Willow Cove core. It is expected that Golden Cove will improve IPC, unlike Willow Cove which actually had a tiny reduction compared to Sunny Cove; this is also the same core that is featured in the upcoming Alder Lake CPU. According to our information, Sapphire Rapids CPUs will have 56 cores, but we strongly suspect that the actual silicon has 60 cores and 4 have been disabled. This is likely done because of poor yields.
One feature of the Golden Cove core that will be returning to Intel’s server and datacenter platform is Bfloat16. And I say returning because it was featured on the 14nm Cooper Lake but not on the 10nm Ice Lake. We don’t know if there are any other instructions being added, we just know of Bfloat16.
Intel will also be moving to PCIe 5.0 and DDR5. Sapphire Rapids will have up to 80 lanes and CXL, which is fairly competitive against AMD’s IO on its Rome platform, which offers more lanes but only at PCIe 4.0 speeds. However, this seems to only be possible with specific SKUs; for other SKUs, only 64 lanes are available. Sapphire Rapids supports up to 4800 MHz DDR5 and has 8 memory channels per CPU. It of course also supports Optane memory.
So far all of this has been pretty standard. I’m fairly certain at least some of this has already been reported on; at the very least, we have been for some time expecting PCIe 5.0 and DDR5 on Sapphire Rapids. Of course, we wouldn’t be making an exclusive if we didn’t have any exclusive details to share. According to our information, Sapphire Rapids will be using a multi tile (that is, MCM or chiplet) design and will support HBM2. The former innovation represents Intel catching up to AMD, the latter might be a case where Intel is finally ahead of AMD for once (but I wouldn’t count on it).
Based on the info we have, we expect Sapphire Rapids to have 4 CPU tiles and each should have 14 enabled cores; if the whole CPU has 60 physical cores, then each tile should have 15 physical cores with one disabled on each. You may notice that we’re kind of speculating here, and that’s mostly because our documents don’t elaborate much on this “multi tile” design. This is the same kind of language used to describe Arctic Sound, which is an MCM or chiplet design like Naples or Rome. So, we’re pretty sure Sapphire Rapids is MCM or chiplets, we just don’t have many details. Furthermore, if Sapphire Rapids lacks an IO die, it is arguable that it’s not chiplet based but MCM; keep in mind however that this is just semantics.
Alongside 4 CPU dies, there can exist 4 HBM2e stacks with a total capacity of up to 64 GB and a total bandwidth of up to 1 TB/s. This kind of bandwidth could enable some impressive performance, let down only by the 10nm(+++) node which restricts Intel’s volume and CPU performance. Additionally, the HBM2e can work with the DDR5 memory in several modes: flat, caching/2LM, and hybrid.
This all sounds great, but there’s two problems Sapphire Rapids will encounter. One issue is the TDP, for which we actually have two different figures: 300 and 400 watts. We believe both figures are correct but likely refer to two different SKUs. So, for Sapphire Rapids’s best case, we’re looking at a 400 watt TDP which is fairly uncomfortable. The highest end Rome processor, the Epyc 7H12, caps out at 280 watts, lower still than the more acceptable 300 watt figure.
One other problem for Sapphire Rapids is the fact that it is supposed to debut at the end of 2021. Or, that is, the Eagle Stream platform initially launches at the end of 2021. The first implementation of Sapphire Rapids will be in the Aurora supercomputer which is due for early 2021, but that’s a special order from the Department of Energy, so it’s not too surprising that the larger market gets access several months later. However, as a product, this pits Sapphire Rapids not against Rome or even Milan, but Genoa, AMD’s 5nm server CPU that also supports PCIe 5.0 and DDR5. Even if Sapphire Rapids launches first, it will not matter. You’ll see why.
So, that’s about all the info we have. The most exciting thing coming out of Sapphire Rapids is the multi tile design. It is about time Intel finally caught up to AMD which has been using chiplets since 2019 and MCM since 2017. The addition of HBM2 is also cool, though I should note that rumors concerning AMD doing a similar thing have been around for some time. Still, Sapphire Rapids will probably be Intel’s most important product of 2021.
Like always, we’ll keep you guys updated on Sapphire Rapids if we get more information.
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