AMD EPYC Genoa Leak: 128 Cores, 16 CCDs, 12-Channel DDR5-5200, Die Sizes

We created a new mockup of Genoa, based on our source, using @ExecuFix’s mockup as a template

Information about AMD’s upcoming Genoa Zen4-based server CPU architecture has been churning in the rumor mill for a while now. We’ve seen a leaked AMD Embedded Product Roadmap reported by VideoCardz, that shows Genoa (EPYC 7004) launching likely Spring 2022, utilizing the Zen4 architecture, and containing “>64” cores and “120-280+” TDP. The launch date was corroborated by AMD’s CTO Mark Papermaster during EPYC Milan’s launch, saying Genoa was “well underway and on track to come to market in 2022.”

Leaked AMD Embedded Product Roadmap. [Image Credit: VideoCardz]

We’ve also seen reports by ExecutableFix on Twitter claiming 96 cores and a collection of important system specifications, such as 12-channel DDR5-5200, PCIe 5.0, SP5 (LGA-6096) socket, with a TDP tipping 320W. Critically, the roadmap explicitly states “>64” cores, which means 96 is entirely reasonable. The “280+” TDP shows that the 320W mentioned by @ExecuFix can be correct as well. The top end Milan EPYC 7763 pushes 280W TDP, so a “+” tacked on was a coy way to suggest higher-end parts, especially since Genoa and Zen4 will be on a more power efficient TSMC 5nm.

Which brings us to our leak. I’ve made a table to break it down a bit more visually for us:

EPYC Family NameNaplesRomeMilanGenoa
Platform NameSP3SP3SP3SP5
SocketLGA 4094LGA 4094LGA 4094LGA 6096
Max Core Count326464128
Max L3 Cache64 MB256 MB256 MB512 MB
Max Chiplets4 CCDs8 CCDs + 1 IOD8 CCDs + 1 IOD16 CCDs + 1 IOD
CPU Chiplet Node14nm GloFo7nm TSMC7nm TSMC5nm TSMC
Chiplet Size212.97 mm²~74 mm²~74 mm²~69 mm²
IOD NodeN/AGloFo 14nmGloFo 14nm?TSMC 6nm
IOD SizeN/A~416 mm²~416 mm²?~263 mm²
Memory Support8-Channel8-Channel8-Channel12-Channel
Memory SpeedDDR4-2666DDR4-3200DDR4-3200DDR5-5200
(New information underlined, estimated info in italics)

We had received information pertaining to Genoa and had a hard time believing it initially, as 128 cores is a large jump over the more-reserved rumor of 96 cores going around. However, today’s Milan-X leak, which confirmed our “ZenX” leak from two and half years ago, certainly clarified things. In Jim’s EPYC Update video from back then, our information was basically only that ZenX was a thing and that it was being kept very close to the chest. Speculation back and forth behind the scenes was that it could be chip stacking. It could have been CPU+GPU+RAM, 3D stacking, an active interposer, we weren’t sure. Milan-X with “X3D” Packaging (as mentioned during AMD’s Financial Analyst Day on March 5th, 2020) could be a key technology forerunner for Genoa.

Granted, VideoCardz‘s source said Milan-X was not focused on increasing core count, but that doesn’t preclude the technology from aiding Genoa to reach higher core counts, such as the aforementioned 128 cores that our source claims. This also still works out with @ExecuFix’s 96-core leak, as that could be a mid-range Genoa design, as we know EPYC Milan utilizes a range of 4 to 8 CCDs to create the range of SKUs for its line-up. Genoa can very easily have a 12 CCD variant in the mix, and would help keep the 16 CCD variant under wraps.

Our mockup of Genoa, based on our source, using @ExecuFix’s mockup as a template

The X3D Packaging, if used in Genoa, throws our mockup off a bit though. Instead of four CDDs side-by-side per quadrant, it could well be two stacks of CCDs per quadrant utilizing the layout we’ve seen with Rome and Milan.

Looking through the rest of our leak, we get die sizes of ~69 mm² on TSMC 5nm for the Zen4 chiplets and ~263 mm² on TSMC 6nm for the IOD. The size reductions were a given due to the die shrink, but the most notable is the massive 37% reduction in IO die size, enabled by the switch from GlobalFoundries to TSMC’s 6nm node. With AMD’s recently revised seventh amendment to their Wafer Supply Agreement with GlobalFoundries, which notably drops all exclusivity agreements (outside the minimum order requirements for 2022, 2023, and 2024 of course), this certainly lines up with AMD selecting TSMC for manufacturing of the next-gen IODs for EPYC and Ryzen. 12/14nm nodes can still fill previous-gen, embedded, or specialty (Chromebook) CPU orders and serve as cheap competitors to Intel’s low-end CPUs, without AMD having to waste modern-node wafers on small dual or quad core CPUs for slim margins, just to flesh out a lineup.

Intel Xeon Sapphire Rapids package (Engineering Sample), [Image Source: YuuKi_AnS on Bilibili]

AMD EPYC Genoa will be competing with Intel’s Sapphire Rapids 4th Generation Xeon server CPU, which boasts 56 cores and 8-Channel DDR5-4800. Those mere 56 cores require four 15-core Golden Cove dies at 372mm² each, fabbed on 10nm++ and glued together with Intel’s EMIB (Embedded Multi-Die Interconnect Bridge) technology, and has 112 MB of L3 cache. While these specs line up fairly well with AMD’s current Milan 7003-series EPYC CPUs, those CPUs have already launched, whereas Sapphire Rapids isn’t due until 2022, where it will be met head-on with Genoa, which will likely be cheaper to manufacture and clock higher at better TDPs; a veritable hat trick in the semiconductor industry for sure.

It’s still unclear whether the exact source of our leaked info is from an insider, or just industry-adjacent, but we’ve had extremely accurate information from them in the past. However, still take this all as speculative rumor and with a large dose of salt, of which most readers of industry leaks should have on ample supply already.

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